|
The VEX prefix (from "vector extensions") and VEX coding scheme are comprising an extension to the x86 and x86-64 instruction set architecture for microprocessors from Intel, AMD and others. ==Features== The VEX coding scheme allows the definition of new instructions and the extension or modification of previously existing instruction codes. This serves the following purposes: * The opcode map is extended to make space for future instructions. * It allows instruction codes to have up to five operands, where the original scheme allows only two operands (in rare cases three operands). * It allows the size of SIMD vector registers to be extended from the 128-bits XMM registers to 256-bits registers named YMM. There is room for further extensions of the register size in the future. * It allows existing two-operand instructions to be modified into non-destructive three-operand forms where the destination register is different from both source registers. For example, ''c = a + b'' instead of ''a = a + b'' (where register ''a'' is changed by the instruction). The VEX prefix ''replaces'' the most commonly used instruction prefix bytes and escape codes. In many cases, the number of prefix bytes and escape bytes that are replaced is the same as the number of bytes in the VEX prefix, so that the total length of the VEX-encoded instruction is the same as the length of the legacy instruction code. In other cases, the VEX-encoded version is longer or shorter than the legacy code. In 32-bit mode VEX encoded instructions can only access the first 8 YMM/XMM registers; the encodings for the other registers would be interpreted as the legacy LDS and LES instructions that are not supported in 64-bit mode. The two-byte VEX prefix contains the following components: * The bit, R, similar to the REX.R prefix bit used in the x86-64 instruction set extension. * Four bits named v, specifying a second source register operand. * A bit named L specifying 256-bit vector length. * Two bits named p to replace operand size prefixes and operand type prefixes (66, F2, F3). The three-byte VEX prefix additionally contains: * The three bits, X; B; and W, also similar to the corresponding bits in the REX prefix. * Five bits named m. Two of the m bits are used for replacing existing escape codes and for specifying the length of the instruction. The remaining three m bits are reserved for future use, such as specifying vector lengths >256 bits, specifying different instruction lengths, or extending the opcode space, however as of 2013, Intel decided to introduce a new encoding scheme, the EVEX prefix, rather than expand the remaining m bits. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「VEX prefix」の詳細全文を読む スポンサード リンク
|